Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches
IEEE Transactions on Computers
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This paper discusses the reconfiguration problem of two-dimensional degradable VLSI/WSI processor arrays under the row and column rerouting constraints. Some algorithms have been proposed for this problem; however, they are not designed to be implemented in hardware for self-reconfigurable systems. In this paper, we propose an efficient reconfiguration algorithm for degradable processor arrays based on the simple schemes of row and column rerouting. For the aim of realizing self-reconfiguration, the new rerouting schemes employed in our methodare designed to be executed using only local information from neighboring processors. The performances of proposed algorithm are compared with previous studies and it indicates that the proposed algorithm achieves better results in terms of harvest, degradation.