An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors

Authors:
Yung-Yuan Chen;Ching-Hwa Cheng;Jwu-E Chen
Affiliations:
-;-;-
Venue:
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Year:
1995

Citing 1
Cited 1

An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors

EDCC-1 Proceedings of the First European Dependable Computing Conference on Dependable Computing

A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors

IEEE Transactions on Computers

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Abstract

In this paper, we propose a new diagnosis scheme to detect and locate the switching network defects faults in fault-tolerant VLSI/WSI array processors. Error in testing that causes a good PE, switch and link to be considered as a bad one is called "killing error". The issue of killing error in testing is addressed and the probability of killing error for our diagnosis scheme is analyzed and shown to be extremely low. The significance of this approach is the ability to detect and locate the multiple faults in switches and links with low testing circuit overhead, and to offer good testing quality and less diagnosis time. The diagnosis time of switching network is O(N), where N is the dimension of mesh array.