Fault clustering in deep-submicron CMOS processes

Authors:
Jan Schat
Affiliations:
NXP Semiconductors Germany
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2008

Citing 3
Cited 1

On yield, fault distributions, and clustering of particles

IBM Journal of Research and Development
Reducing the complexity of defect level modeling using the clustering effect

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product

IBM Journal of Research and Development

Efficient memory repair using cache-based redundancy

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

The fraction of ICs that pass all production tests but fail in the application is called the defect level. Defect levels depend on the average number of defects per IC, and also on the clustering of these defects. High clustering leads to a higher yield and a lower defect level. This paper compiles the coefficients for defect clustering using research findings from 1970 until 2001. Because recent data for deep submicron processes are missing in the literature, the clustering coefficient has been calculated using scan fail distributions of ICs in a 180 nm process. Clustering coefficients show a steady trend towards higher defect clustering. This is beneficial, but it is probably not sufficient to achieve today's ambitious target of 'zero defects'.