Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Error Correcting Strategy for High Speed and High Density Reliable Flash Memories
Journal of Electronic Testing: Theory and Applications
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Efficient Spare Allocation for Reconfigurable Arrays
IEEE Design & Test
A Fault-Driven, Comprehensive Redundancy Algorithm
IEEE Design & Test
LPRAM: a novel low-power high-performance RAM design with testability and scalability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Memories are among the densest integrated circuits that can be fabricated and therefore, have the highest rate of defects. This paper discusses an efficient technique for designing low cost high defect tolerant RAM chips. A 25% improvement in the yield is presented. The paper proposes a scheme that selects the right redundancy in memory designs driven by the fabrication cost and the yield. The new memory chip design technique fills the gap between the existing all-or-none extremes with memories. The area is sacrificed for these performance improvements, for significant power savings as well as for the significant improvement in the yield.