A Comphrehensive Networks-on-Chip Simulator for Error Control Explorations

Authors:
Qiaoyan Yu;Meilin Zhang;Paul Ampadu
Affiliations:
University of Rochester, Rochester, NY;University of Rochester, Rochester, NY;University of Rochester, Rochester, NY
Venue:
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Year:
2011

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Abstract

Error control is imperative for reliable Networks-on-Chip (NoCs) design. In this demo session, we will present a CAD tool---a flexible and parallel NoC simulator. Our simulator evaluates the impact of different error control mechanisms on NoC performance and energy consumption in various noise and traffic injection scenarios. Our message passing interface language-based simulator can be executed on multiprocessors or server clusters. Multiple built-in blocks provide flexibility to evaluate different error control methods.