Genetic programming: on the programming of computers by means of natural selection
Genetic programming: on the programming of computers by means of natural selection
DARWIN: CMOS opamp synthesis by means of a genetic algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Evolution using genetic programming of a low-distortion, 96 decibel operational amplifier
SAC '97 Proceedings of the 1997 ACM symposium on Applied computing
Genetic Programming III: Darwinian Invention & Problem Solving
Genetic Programming III: Darwinian Invention & Problem Solving
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
Automated Analog Circuit Sythesis Using a Linear Representation
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Genetic Programming IV: Routine Human-Competitive Machine Intelligence
Genetic Programming IV: Routine Human-Competitive Machine Intelligence
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
GECCO '96 Proceedings of the 1st annual conference on Genetic and evolutionary computation
GECCO '96 Proceedings of the 1st annual conference on Genetic and evolutionary computation
GRACE: generative robust analog circuit exploration
EuroGP'06 Proceedings of the 2006 international conference on Applications of Evolutionary Computing
Explorations in design space: unconventional electronics designthrough artificial evolution
IEEE Transactions on Evolutionary Computation
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In this paper, a new method for evolving simple electronic circuits is discussed, with the aim of improving the reliability and performance of basic circuit blocks. Next-generation CMOS device models will be used in the simulation of circuits. Circuits are mapped to a grid layout which reflects the appearance of conventional schematic blocks. The performance of the system at designing passive low-pass filters is discussed, with an outline given of the intended future steps, towards the goal of integrating sub 100 nm MOSFET models into the circuits.