Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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An automated top-down design flow to achieve physical design of Analog/Mixed-Signal Systems-on-Chip (AMS-SoCs) is difficult, especially for nano-CMOS. Process variation effects have profound impact on the performance of silicon versus layout design. In this paper metamodels, (surrogate models) and Particle Swarm Optimization (PSO) have been combined in an automated physical design flow for fast design exploration of AMS-SoCs. Neural network based non-polynomial metamodels that handle large numbers of design parameters, are used to predict the statistical process variation effects instead of exhaustive Monte Carlo simulations. The PSO algorithm is used for optimization of the AMS-SoC components using their metamodels instead of the actual circuit. The PSO algorithm followed a two step approach: local and global. The physical design of a Phase Locked Loop (PLL) is considered as a case study circuit. The proposed design flow is approximately 5 times faster while the error is under 2% compared to the Monte Carlo analysis.