Optimising variability tolerant standard cell libraries

Authors:
James A. Hilder;James Alfred Walker;Andy M. Tyrrell
Affiliations:
Intelligent Systems Group, Department of Electronics, University of York, Heslington, York, UK;Intelligent Systems Group, Department of Electronics, University of York, Heslington, York, UK;Intelligent Systems Group, Department of Electronics, University of York, Heslington, York, UK
Venue:
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
Year:
2009

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Abstract

This paper describes an approach to optimise transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant to the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced SPICE models based on 3D-atomistic simulations, a Genetic Algorithm optimises the device widths within a circuit using a multiobjective fitness function. The results show the impact of threshold voltage variation can be reduced by optimising transistor widths, and suggest a similar method could be extended to the optimisation of larger circuits.