Power Dissipation Reductions with Genetic Algorithms

Authors:
Eiichi Takahashi;Masahiro Murakawa;Yuji Kasai;Tetsuya Higuchi
Affiliations:
-;-;-;-
Venue:
EH '03 Proceedings of the 2003 NASA/DoD Conference on Evolvable Hardware
Year:
2003

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Abstract

Two cases of power dissipation reduction with Pos-tfabrication adjustment using genetic algorithms Are introduced in this paper. The first is a 1GHz ALUimplementation, where power consumption has beenreduced by 54% through clock-timing adjustment. Thesecond case is the IF (Intermediate Frequency) filteranalog LSI used in cellular phones, where the reduction in power dissipation is realized by circuit parameteradjustment. The IF filter has been widely used incommercial cellular phones since 2001.