Testing of Digital Systems
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
A general framework for spatial correlation modeling in VLSI design
Proceedings of the 44th annual Design Automation Conference
Towards trojan-free trusted ICs: problem analysis and detection scheme
Proceedings of the conference on Design, automation and test in Europe
Randomization Based Probabilistic Approach to Detect Trojan Circuits
HASE '08 Proceedings of the 2008 11th IEEE High Assurance Systems Engineering Symposium
A region based approach for the identification of hardware Trojans
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Hardware Trojan detection using path delay fingerprint
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Hardware Trojan horse detection using gate-level characterization
Proceedings of the 46th Annual Design Automation Conference
Performance of delay-based Trojan detection techniques under parameter variations
HST '09 Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust
A Survey of Hardware Trojan Taxonomy and Detection
IEEE Design & Test
On Generating Vectors for Accurate Post-Silicon Delay Characterization
ATS '11 Proceedings of the 2011 Asian Test Symposium
A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Trojan Detection via Calibration of Process Variations
ATS '12 Proceedings of the 2012 IEEE 21st Asian Test Symposium
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One of the growing issues in IC design is how to establish trustworthiness of chips fabricated by untrusted vendors. Such process, often called Trojan detection, is challenging since the specifics of hardware Trojans inserted by intelligent adversaries are difficult to predict and most Trojans do not affect the logic behavior of the circuit unless they are activated. Also, Trojan detection via parametric measurements becomes increasingly difficult with increasing levels of process variations. In this paper we propose a method that maximizes the resolution of each path delay measurement, in terms of its ability to detect the targeted Trojan. In particular, for each Trojan, our approach accentuates the Trojan's impact by generating a vector that sensitizes the shortest path passing via the Trojan's site. We estimate the minimum number of chips to which each vector must be applied to detect the Trojan with sufficient confidence for a given level of process variations. Finally, we demonstrate the significant improvements in effectiveness and cost provided by our approach under high levels of process variations. Experimental results on several benchmark circuits show that we can achieve dramatic reduction in test cost using our approach compared to classical path delay testing.