Statistical Test Compaction Using Binary Decision Trees
IEEE Design & Test
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Study of an Electrical Setup for Capacitive MEMS Accelerometers Test and Calibration
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Electrical calibration of spring-mass MEMS capacitive accelerometers
Proceedings of the Conference on Design, Automation and Test in Europe
Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Electronic Testing: Theory and Applications
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Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel ...