Optimal ordering of analog integrated circuit tests to minimize test time
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Test Generation for Accurate Prediction of Analog Specifications
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Specification Test Compaction for Analog Circuits and MEMS
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Alternate Electrical Tests for Extracting Mechanical Parameters of MEMS Accelerometer Sensors
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Statistical Test Compaction Using Binary Decision Trees
IEEE Design & Test
Non-RF to RF Test Correlation Using Learning Machines: A Case Study
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
The minimum consistent subset cover problem and its applications in data mining
Proceedings of the 13th ACM SIGKDD international conference on Knowledge discovery and data mining
Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Maintaining Accuracy of Test Compaction through Adaptive Re-learning
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Top-down induction of decision trees classifiers - a survey
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
Nonlinear decision boundaries for testing analog circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimizing production test time to detect faults in analog circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Stringent quality requirements for integrated, heterogeneous systems have led designers and test engineers to mandate large sets of tests to be applied to these systems, which, in turn, have resulted in increased test cost. However, many of these tests are unnecessary (i.e., redundant), since their outcomes can be reliably predicted using results from other applied tests. A methodology for identifying the redundant tests of an integrated, heterogeneous system that has only binary pass-fail test data is described. This methodology uses decision trees, Boolean minimization, and satisfiability as core components. Feasibility is empirically demonstrated using test data from two commercially fabricated systems, namely, a high-speed serializer/deserializer (HSS) and a phase-locked loop (PLL). Our analysis of test data from 38,000 HSS and 22,000 PLL circuits show that 14 out of 40 HSS tests and 11 out of 36 PLL tests are redundant.