Test Metrics for Analog Parametric Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Testing Techniques for RF Wireless Transceivers
IEEE Design & Test
Test Development Through Defect and Test Escape Level Estimation for Data Converters
Journal of Electronic Testing: Theory and Applications
A Low-Noise Amplifier with Integrated Current and Power Sensors for RF BIST Applications
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Proceedings of the conference on Design, automation and test in Europe
Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asymptotic Probability Extraction for Nonnormal Performance Distributions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adaptive test elimination for analog/RF circuits
Proceedings of the 46th Annual Design Automation Conference
Evaluation of analog/RF test measurements at the design stage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Enrichment of limited training sets in machine-learning-based analog/RF test
Proceedings of the Conference on Design, Automation and Test in Europe
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We present a general method to evaluate RF Built-In Self-Test (BIST) techniques during the design stage. In particular, the adaptive kernel estimator is used to construct an estimate of the joint probability density function of the performances of the RF device under test and the actual BIST measurements. The density is sampled to generate a large volume of new data, which is subsequently used to estimate the relevant test metrics with parts per million (ppm) accuracy given the BIST limits. Thus, the BIST limits can be set to obtain the desired trade-offs between different test metrics. The proposed method aims to assist designers in comparing RF BIST techniques on the basis of accurately calculated test metrics and to provide information for early BIST refinements, thus reducing the design cycles. The method is demonstrated for a previously published RF BIST technique [1] applied to an LNA.