A general method to evaluate RF BIST techniques based on non-parametric density estimation
Proceedings of the conference on Design, automation and test in Europe
Evaluation of analog/RF test measurements at the design stage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits
Proceedings of the 49th Annual Design Automation Conference
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Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel ...