Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits

Authors:
Chin-Cheng Kuo;Wei-Yi Hu;Yi-Hung Chen;Jui-Feng Kuan;Yi-Kan Cheng
Affiliations:
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan;Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan, and National Taiwan University, Taipei, Taiwan;Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan;Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan;Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan
Venue:
Proceedings of the 49th Annual Design Automation Conference
Year:
2012

Citing 11
Cited 0

A method for linking process-level variability to system performances

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Monte Carlo-Alternative Probabilistic Simulations for Analog Systems

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Projection-based performance modeling for inter/intra-die variations

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System Simulations

VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast statistical analysis of process variation effects using accurate PLL behavioral models

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Behavioral modeling for calibration of pipeline analog-to-digital converters

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Why quasi-Monte Carlo is better than monte carlo or latin hypercube sampling for statistical circuit analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Efficient LHS-Based Yield Analysis of Analog Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper proposes efficient trimmed-sample Monte Carlo (TSMC) methodology and novel yield-aware design flow for analog circuits. This approach focuses on "trimming simulation samples" to speedup MC analysis. The best possible yield and the worst performance are provided "before" MC simulations such that designers can stop MC analysis and start improving circuits earlier. Moreover, this work can combine with variance reduction techniques or low discrepancy sequences to reduce the MC simulation cost further. Using Latin Hypercube Sampling as an example, this approach gives 29x to 54x speedup over traditional MC analysis and the yield estimation errors are all smaller than 1%. For analog system designs, the proposed flow is still efficient for high-level MC analysis, as demonstrated by a PLL system.