Statistical behavioral modeling and characterization of A/D converters
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
CMOS data converters for communications
CMOS data converters for communications
A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A simple technique for fast digital background calibration of A/D converters
EURASIP Journal on Advances in Signal Processing
Digital background-calibration algorithm for "split ADC" architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Frequency-dependent sampling linearity
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits
Proceedings of the 49th Annual Design Automation Conference
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In this paper, a design flow for the design of calibrated pipeline analog-to-digital converters (ADCs), and a framework for their behavioral modeling is presented. The model includes also second order effects such as nonlinearities and linear and non-linear memory errors, thus allowing fast and accurate simulations of the ADC behavior. In this way, background calibration techniques can be simulated during the design phase, allowing the optimization of ADC performance even under process variations. The design flow can be used to extract information about sensitivity to operating and environmental conditions, post-calibration performance and also design yield, by extracting a database of Monte Carlo realizations of the ADC stages, so that it can be employed to optimize system and circuit design. Simulations using a O.13-µm CMOS technology show an accuracy of the model as high as 17 bits.