Numerical recipes in C (2nd ed.): the art of scientific computing
Numerical recipes in C (2nd ed.): the art of scientific computing
Adaptive filter theory (3rd ed.)
Adaptive filter theory (3rd ed.)
Matrix computations (3rd ed.)
"Split ADC" calibration for all-digital correction of time-interleaved ADC errors
IEEE Transactions on Circuits and Systems II: Express Briefs
Behavioral modeling for calibration of pipeline analog-to-digital converters
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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The "split ADC" architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms.