The Reliability of Approximate Testability Measures
IEEE Design & Test
ACM Transactions on Information Systems (TOIS)
Defect-Oriented Test Scheduling
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Hi-index | 14.99 |
A simple algorithm that shows how to optimally schedule the test-application and the signature-analysis phases of VLSI testing is presented. The testing process is broken into subintervals, the signature is analyzed at the end of each subinterval, and future tests are aborted if the circuit is found to be faulty, thus saving test time. The mathematical proofs associated with the algorithm are given.