On Static Test Compaction and Test Pattern Ordering for Scan Designs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test vector decomposition-based static compaction algorithms for combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Test set compaction is a fundamental problem in digital system testing. In recent years, many competitive solutions have been proposed, most of which based on heuristics approaches. This paper studies the application of set covering models to the compaction of test sets, which can be used with any heuristic test set compaction procedure. For this purpose, recent and highly effective set covering algorithms are used. Experimental evidence suggests that the size of computed test sets can often be reduced by using set covering models and algorithms. Moreover, a noteworthy empirical conclusion is that it may be preferable not to use fault simulation when the final objective is test set compaction.