Computer - IEEE Centennial: the state of computing
The C programming language
Test Routines Based on Symbolic Logical Statements
Journal of the ACM (JACM)
Logical Design of Digital Systems
Logical Design of Digital Systems
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
High-speed concurrent fault simulation with vectors and scalars
DAC '80 Proceedings of the 17th Design Automation Conference
Methods for generalized deductive fault simulation
DAC '80 Proceedings of the 17th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Hierarchical modeling and simulation in VISTA
DAC '79 Proceedings of the 16th Design Automation Conference
A hierarchical approach test vector generation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
What is the path to fast fault simulation?
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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This paper presents techniques for simulating directly from a hierarchical circuit description without flattening to the level of primitives. An overview of traditional fault simulation techniques is followed by details of the hierarchical techniques. The fault model is shown to be decoupled from the simulator programs through the use of a fault library. The fault library allows the user to mix both functional and technology-dependent fault models, which allows fault simulation and consequently test coverage estimation early in the design, with refinements in the fault model and test coverage as the design progresses. Thus testing problems can be detected early in the design process while they are much easier to correct. The circuit description language, SCALD, and the fault library language are described and illustrated with examples. The simulator initialization and execution phases are discussed in detail with emphasis on the unique data structures necessary for hierarchical simulation. The hierarchy provides a framework for an adaptive evaluation technique that speeds the evaluation of faulty machines. Initial performance measurements and experiences with the simulator indicate that hierarchical fault simulation is superior to traditional techniques.