Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
New methods of improving parallel fault simulation in synchronous sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A fast, accurate, and non-statistical method for fault coverage estimation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On Non-Statistical Techniques for Fast Fault Coverage Estimation
Journal of Electronic Testing: Theory and Applications
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This paper discusses the important role of fault grouping in a parallel 32-bit fault simulator such as PROOFS. Three algorithms are presented which dynamically order the fault list during fault simulation to determine how the faults get grouped together. The dynamic fault grouping algorithms were incorporated into PROOFS and tested on benchmark circuits. The algorithms showed a marked reduction in the number of faulty circuit gate evaluations (compared to a static fault grouping) for almost all of the circuits with more than 20 flip-flops. For the largest benchmark circuit, s35932, all of the algorithms showed at least a 39% reduction in the number of faulty circuit gate evaluations and at least a 55% speedup in simulation time.