Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Automatic test generation using genetically-engineered distinguishing sequences
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Fault coverage estimation by test vector sampling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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