Feedback-testing by using multiple input signature registers
Journal of Electronic Testing: Theory and Applications
A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Enhancing high-level control-flow for improved testability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Testability analysis and insertion for RTL circuits based on pseudorandom BIST
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Design for Testability Using Architectural Descriptions
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
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A high-level test synthesis methodology based onBIST is proposed. This methodology targets the conditionalif-then-else statements in a behavioral descriptionbecause such statements can introduce testabilityproblems in the resulting circuit. How well the operationsin each branch of a conditional statement can betested depends on the probability of taking each branchand the quality of the test patterns used in each branch.Behavioral modifications are presented that can resolvethese testability issues. Experimental results from threepractical examples show that this technique is effective.