Selecting Software Test Data Using Data Flow Information
IEEE Transactions on Software Engineering
An Applicable Family of Data Flow Testing Criteria
IEEE Transactions on Software Engineering
A Formal Evaluation of Data Flow Path Selection Criteria
IEEE Transactions on Software Engineering
A Fortran language system for mutation-based software testing
Software—Practice & Experience
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Comparison of Some Structural Testing Strategies
IEEE Transactions on Software Engineering
From Specification Validation to Hardware Testing: A Unified Method
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Validation Fault Model for Timing-Induced Functional Errors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
An efficient control-oriented coverage metric
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A coverage metric for the validation of interacting processes
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Journal of Electronic Testing: Theory and Applications
Coverage driven high-level test generation using a polynomial model of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An approach to testing commercial embedded systems
Journal of Systems and Software
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Behavioral HDL descriptions are commonly used to capture the high-level functionality of a hardware circuit for simulation and synthesis. The manual process of creating a behavioral description is error prone, so significant effort must be made to verify the correctness of behavioral descriptions. Simulation-based validation and formal verification are both techniques used to verify correctness. We investigate validation because formal verification techniques are frequently intractable for large designs. The first step toward a behavioral validation technique is the development of a validation fault coverage metric which can be used to evaluate the likelihood of design defect detection with a given test sequence.We propose a validation fault coverage metric which is based on an analysis of the control data flow description associated with the behavior. The proposed metric identifies a subset of paths through the data flow which must be traversed during testing to detect faults. The proposed metric is a tractable compromise between the statement coverage metric which requires only that each statement be executed, and the path coverage metric which requires that all data flow paths be executed. Data flow paths are identified based on the relative code locations of definitions and uses of variables which may be assigned incorrectly due to a design error. We propose an efficient method to compute all data flow paths which must be traversed, and we generate coverage results for several benchmark VHDL circuits for comparison to other approaches.