AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-frequency custom CMOS S/390 microprocessor
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Functional verification of the CMOS S/390 parallel enterprise server G4 system
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Custom S/390 G5 and G6 microprocessors
IBM Journal of Research and Development
Self-timed interface for S/390 I/O subsystem interconnection
IBM Journal of Research and Development
IBM eServer z900 I/O subsystem
IBM Journal of Research and Development
Coupling I/O channels for the IBM eServer z900: reengineering required
IBM Journal of Research and Development
Hyper-acceleration and HW/SW co-verification as an essential part of IBM eServer z900 verification
IBM Journal of Research and Development
Reliability, availability, and serviceability (RAS) of the IBM eServer z990
IBM Journal of Research and Development
The GNU 64-bit PL8 compiler: toward an open standard environment for firmware development
IBM Journal of Research and Development
The z990 first error data capture concept
IBM Journal of Research and Development
Accelerating system integration by enhancing hardware, firmware, and co-simulation
IBM Journal of Research and Development
IBM eServer z990 improvements in firmware simulation
IBM Journal of Research and Development
Enhanced I/O subsystem recovery and availability on the IBM System z9
IBM Journal of Research and Development
Open-standard development environment for IBM System z9 host firmware
IBM Journal of Research and Development
Advanced firmware verification using a code simulator for the IBM System z9
IBM Journal of Research and Development
RAS design for the IBM eServer z900
IBM Journal of Research and Development
IBM eServer z900 system microcode verification by simulation: the virtual power-on process
IBM Journal of Research and Development
Hyper-acceleration and HW/SW co-verification as an essential part of IBM eServer z900 verification
IBM Journal of Research and Development
IBM system z10 firmware simulation
IBM Journal of Research and Development
Concurrently update the scan-initialization data of a processor core
IBM Journal of Research and Development
IBM Parallel Sysplex design for the IBM z196 system
IBM Journal of Research and Development
Firmware verification and simulation in IBM zEnterprise 196
IBM Journal of Research and Development
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An IBM eServer zSeries™ system uses various types of microcode (firmware) that implement functions such as the execution of complex instructions in the CPUs, I/O operations performed by the system assist processors (SAPs), the management of logical partitions (LPARs), and control by the support element (SE). Each microcode component must be verified by itself and in conjunction with the others. Tight development schedules and a very limited supply of expensive engineering hardware make it desirable to perform this verification in a simulation environment. For the development of the z900, a new microcode simulator, the z/CECSIM (Central Electronic Complex Simulator), was successfully implemented. Several microcode components are connected in a single simulation environment, thereby allowing an unprecedented amount of development, integration, and testing without the use of engineering hardware. z/CECSIM creates a virtual zSeries CEC on VM/ESA® or z/VM™ that allows the simulation of zSeries microcode. It executes the instruction stream as completely as possible on the underlying hardware. Only instructions that are newly introduced with the system being developed or that perform a microcode-internal function are simulated. Additional software models mimic the behavior of I/O and coupling channels. An optional SE connection allows verification of interactions between the CEC and its support element.