Run-control and service element code simulation for the S/390 microprocessor
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
The IBM engineering verification engine
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
System-Level Verification -- A Comparison of Approaches
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
System control structure of the IBM eServer z900
IBM Journal of Research and Development
IBM eServer z900 system microcode verification by simulation: the virtual power-on process
IBM Journal of Research and Development
z/CECSIM: an efficient and comprehensive microcode simulator for the IBM eServer z900
IBM Journal of Research and Development
EDA in IBM: past, present, and future
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improvements in functional simulation addressing challenges in large, distributed industry projects
Proceedings of the 40th annual Design Automation Conference
Accelerating system integration by enhancing hardware, firmware, and co-simulation
IBM Journal of Research and Development
IBM eServer z990 improvements in firmware simulation
IBM Journal of Research and Development
RAS design for the IBM eServer z900
IBM Journal of Research and Development
IBM eServer z900 system microcode verification by simulation: the virtual power-on process
IBM Journal of Research and Development
z/CECSIM: an efficient and comprehensive microcode simulator for the IBM eServer z900
IBM Journal of Research and Development
IBM system z10 firmware simulation
IBM Journal of Research and Development
IBM Parallel Sysplex design for the IBM z196 system
IBM Journal of Research and Development
| Hi-index | 0.00 |
Hardware/software (HW/SW) coverification can considerably shorten the time required for system integration and bring-up. But coverification is limited by the simulation speed achievable whenever hardware models are required to verify hardware and software interactions. Although the use of a general-purpose hardware accelerator as an extremely fast simulator resolves performance aspects, it generates a new set of handling, efficiency, and serviceability demands. This paper describes a means for addressing those demands through the use of one of the largest hyper-acceleration systems created thus far, and describes many new associated features that have been implemented in operating software.