AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Code generation and analysis for the functional verification of micro processors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Symbolic Model Checking
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In this paper an approach is presented for thehierarchical verification of the memory control units, I/O adaptersand processor interconnect units as found in multiprocessorcomputer systems. It is shown how such units could be verifiedbetter and faster by the introduction of random executable timingdiagrams and associated CAD tool support. Furthermore, itis shown how the timing diagrams for the unit network verificationare easily derived from the timing diagrams specified for theunits. The multiprocessor hardware test showed the effectivenessof the proposed verification approach.