Task Allocation for Maximizing Reliability of Distributed Computer Systems
IEEE Transactions on Computers
Static scheduling for synthesis of DSP algorithms on various models
Journal of VLSI Signal Processing Systems
Resource-constrained loop list scheduler for DSP algorithms
Journal of VLSI Signal Processing Systems - Special issue on VLSI design methodologies for digital signal processing systems
IEEE Transactions on Computers
ILP-based cost-optimal DSP synthesis with module selection and data format conversion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Safety and Reliability Driven Task Allocation in Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Efficient Scheduling Algorithms for Real-Time Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Loop-List Scheduling for Heterogeneous Functional Units
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Scheduling Strategies for Master-Slave Tasking on Heterogeneous Processor Platforms
IEEE Transactions on Parallel and Distributed Systems
Mapping and Load-Balancing Iterative Computations
IEEE Transactions on Parallel and Distributed Systems
Rotation scheduling: a loop pipelining algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The master-slave paradigm with heterogeneous processors
IEEE Transactions on Parallel and Distributed Systems
Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraint
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Journal of VLSI Signal Processing Systems
Allocation cost minimization for periodic hard real-time tasks in energy-constrained DVS systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems
Proceedings of the conference on Design, automation and test in Europe
Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP
Journal of Parallel and Distributed Computing
Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Loop scheduling and bank type assignment for heterogeneous multi-bank memory
Journal of Parallel and Distributed Computing
Energy minimization for heterogeneous wireless sensor networks
Journal of Embedded Computing - Design and Optimization for High Performance Embedded Systems
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture
Journal of Signal Processing Systems
Adaptive online energy saving for heterogeneous sensor networks
PDCS '07 Proceedings of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems
Online energy-saving algorithm for sensor networks in dynamic changing environments
Journal of Embedded Computing
Efficent algorithm of energy minimization for heterogeneous wireless sensor network
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Cost Minimization with HPDFG and Data Mining for Heterogeneous DSP
Journal of Signal Processing Systems
Efficient task assignment on heterogeneous multicore systems considering communication overhead
ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Hi-index | 0.00 |
This paper addresses high level synthesis for real-time digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpose architecture synthesis, an important problem is how to assign a proper FU type to each operation of a DSP application and generate a schedule in such a way that all requirements can be met and the total cost can be minimized. We propose a two-phase approach to solve this problem. In the first phase, we solve the heterogeneous assignment problem, i.e., how to assign proper FU types to applications such that the total cost can be minimized while the timing constraint is satisfied. In the second phase, based on the assignments obtained in the first phase, we propose a minimum resource scheduling algorithm to generate a schedule and a feasible configuration that uses as little resource as possible. We prove that the heterogeneous assignment problem is NP-complete. Efficient algorithms are proposed to find an optimal solution when the given DFG is a simple path or a tree. Three other algorithms are proposed to solve the general problem. The experiments show that our algorithms can effectively reduce the total cost compared with the previous work.