Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units
Journal of VLSI Signal Processing Systems
Efficient Assignment and Scheduling for Heterogeneous DSP Systems
IEEE Transactions on Parallel and Distributed Systems
High-level synthesis for DSP applications using heterogeneous functional units
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a new heuristic, concurrent, iterative loop-based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. We assume a library of heterogeneous implementation style based functional units is available. Experiments show that this new heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed recently using an integer linear programming (ILP) model, our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. We compare the solutions generated by the proposed algorithm with the optimal solutions generated by the ILP approach and other recent techniques. We have incorporated this new algorithm into the Minnesota ARchitecture Synthesis (MARS-II) system.