Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Static Rate-Optimal Scheduling of Iterative Data-Flow Programs Via Optimum Unfolding
IEEE Transactions on Computers
Rotation scheduling: a loop pipelining algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Module selection and data format conversion for cost-optimal DSP synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Resource-constrained loop list scheduler for DSP algorithms
Journal of VLSI Signal Processing Systems - Special issue on VLSI design methodologies for digital signal processing systems
Journal of VLSI Signal Processing Systems - Special issue on the 1995 VLSI signal processing workshop
Execution interval analysis under resource constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
VLSI Design Methodologies for Digital Signal Processing Architectures
VLSI Design Methodologies for Digital Signal Processing Architectures
High-Level Synthesis for Real-Time Digital Signal Processing
High-Level Synthesis for Real-Time Digital Signal Processing
High-Level VLSI Synthesis
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
DSP synthesis with heterogeneous functional units using the MARS-II system
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
A technology relative Logic Synthesis and Module Selection system
DAC '81 Proceedings of the 18th Design Automation Conference
Loop-List Scheduling for Heterogeneous Functional Units
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Combinatorial Algorithms: Theory and Practice
Combinatorial Algorithms: Theory and Practice
High-level DSP synthesis using concurrent transformations, scheduling, and allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware-Software partitioning and pipelined scheduling of transformative applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a new heuristic, concurrent, iterativeloop-based scheduling and allocation algorithm for high-level synthesis ofdigital signal processing (DSP) architectures using heterogeneousfunctional units. In a heterogeneous architecture, functional units couldbe either bit-serial or digit-serial or bit-parallel. We assume that alibrary of functional units based on heterogeneous implementation style isavailable. Experiments show that this new heuristic synthesis approachgenerates optimal and near-optimal area solutions. Although optimumsynthesis of such architectures were proposed recently using an integerlinear programming (ILP) model, our method can produce similar solutions inone to two orders of magnitude less time, at the expense of sacrificing thecost optimality. We compare the solutions generated by the proposedalgorithm with the optimal solutions generated by the ILP approach andother recent techniques. We have incorporated this new algorithm into theMinnesota ARchitecture Synthesis (MARS-II) system.