Module selection and data format conversion for cost-optimal DSP synthesis

Authors:
Kazuhito Ito;Lori E. Lucke;Keshab K. Parhi
Affiliations:
Department of Electrical Engineering, University of Minnesota, Minneapolis, MN;Department of Electrical Engineering, University of Minnesota, Minneapolis, MN;Department of Electrical Engineering, University of Minnesota, Minneapolis, MN
Venue:
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Year:
1994

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Abstract

In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear programming (ILP) models which generate a blocked schedule for a DFG with implicit retiming, pipelining, and unfolding while performing module selection and data format conversion. A blocked schedule is a schedule which overlaps multiple iterations of the DFG to guarantee a minimum number of processors. Component modules are selected from a library of processors to minimize cost. Furthermore, we include data format converters between processors of different data formats. In addition, we minimize the unfolding factor of the blocked schedule.