Module selection and data format conversion for cost-optimal DSP synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units
Journal of VLSI Signal Processing Systems
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In this paper we propose a generalized technique to count therequired number of registers in a schedule which supports overlappedscheduling and can be applied to the case where a generaldigit-serial data format is used. This technique is integrated intoan integer linear programming (ILP) model for time-constrainedscheduling. In the ILP model, appropriate processors of certain dataformats are chosen from a library of processors and data formatconverters are automatically inserted between processors of differentdata formats if necessary. Then the required number of registers foreach data format is evaluated correctly by the proposed technique.Hence an optimal architecture for a given digital signal processingalgorithm is synthesized where the cost of registers as well as thecost of processors and data format converters are minimized. It isshown that by including the cost of registers in the synthesis taskas proposed in this paper leads to up to 12.8% savings in the totalcost of the synthesized architecture when compared with synthesisperformed without including the register cost in the total cost.