Adaptive filter theory (2nd ed.)
Adaptive filter theory (2nd ed.)
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
An iterative improvement algorithm for low power data path synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
HEAT: hierarchical energy analysis tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Scheduling techniques to enable power management
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Journal of VLSI Signal Processing Systems - Special issue on the rapid prototyping of application specific signal processors (RASSP) program
Handbook of discrete and computational geometry
Handbook of discrete and computational geometry
Digit-Serial Computation
Pipelined Adaptive Digital Filters
Pipelined Adaptive Digital Filters
Fundamentals of Computer Alori
Fundamentals of Computer Alori
Design tradeoffs in high speed multipliers and FIR filters
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Analytical estimation of signal transition activity from word-level statistics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
51.84 Mb/s 16-CAP ATM LAN standard
IEEE Journal on Selected Areas in Communications
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In this paper, a new two-step algorithm is introduced for power efficient implementation of the folding algorithm transformation of the LMS adaptive FIR filters. The first step handles the scheduling within the folding sets to reduce the switching activity using a greedy algorithm solution for the traveling sales person (TSP) NP-hard problem. The greedy algorithm gives a sub-optimal solution of the TSP problem with low implementation cost. For a typical word-length, and for large folding factors, the projected reduction in switching activity can be as large as 50%. HEAT tool was used to simulate the effect of this reduction using a typical Baugh-Wooley multiplier and the reduction in power consumption for a wireline equalization implementation was found to lie between 25% and 60%. The new algorithm is based on a simple breadth-first search approach and can be easily performed for one time only when the filter is geared to the steady-state mode. The second step involves optimal pipelining of the folded hardware elements for minimum power. The tradeoff between the number of pipelining levels and the power consumption is evaluated. To compensate for the LMS degradation due to pipelining, a 1-pole IIR compensator is introduced in the error loop for relaxed LMS. The IIR based relaxation outperforms the relaxed lookahead pipelining by 2-3 dB of output error. Another feature of the IIR relaxation is the “smoothing” nature of the filter, thus reducing the effective switching activities on the multiplier input. The combined effect of the two techniques can lead to power savings up to 65% compared to a normal folded structure. Simulations for the combined techniques are carried out for the digital subscriber loop channel and significant savings in power are demonstrated.