Design tradeoffs in high speed multipliers and FIR filters

Authors:
C. Nagendra;R. M. Owens;M. J. Irwin
Affiliations:
-;-;-
Venue:
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Year:
1996

Citing 1
Cited 2

High-throughput and low-power DSP using clocked-CMOS circuitry

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

Energy delay analysis of partial product reduction methods for parallel multiplier implementation

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications

Journal of VLSI Signal Processing Systems

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Abstract

In this paper, we study the effects of modified Booth recoding, pipeline granularity and clocking on the speed, power dissipation and transistor count of different types of multipliers and FIR filters. Detailed simulations show that recoding may not always result in an improvement in delay. We propose a way of reducing the activity factor of a Booth multiplier by guarded evaluation. As systems become faster and faster, we can see the trend shifting from pipelining at the level of blocks of bits to bit-level, half-bit-level and even gate-level-pipelining. We run detailed experiments to answer the question of how fine-grain can the depth of pipelining in high-throughput multipliers and filters be made before the increase in power consumption overpowers the speed gain. It is our observation that gate-level pipelining increases power dissipation without improving the speed significantly when compared to half-bit level pipelining.