Programming many-core architectures - a case study: dense matrix computations on the Intel single-chip cloud computer processor

  • Authors:

  • Bryan Marker;Ernie Chan;Jack Poulson;Robert van de Geijn;Rob F.  Van der Wijngaart;Timothy G. Mattson;Theodore E. Kubaska

  • Affiliations:

  • Dept. of Computer Science, The Univ. of Texas at Austin, Austin, Texas 78712;Dept. of Computer Science, The Univ. of Texas at Austin, Austin, Texas 78712;Institute for Computational Engineering and Sciences, The Univ. of Texas at Austin, Austin, Texas 78712;Dept. of Computer Science, The Univ. of Texas at Austin, Austin, Texas 78712;Intel Corporation, Santa Clara, California 95054;Intel Corporation, DuPont, Washington 98327;IntelCorporation, Hillsboro, Oregon 97124

  • Venue:
  • Concurrency and Computation: Practice & Experience
  • Year:
  • 2012

Quantified Score

Hi-index 0.00

Visualization

Abstract

A message passing, distributed-memory parallel computer on a chip is one possible design for future, many-core architectures. We discuss initial experiences with the Intel Single-chip Cloud Computer research processor, which is a prototype architecture that incorporates 48 cores on a single die that can communicate via a small, shared, on-die buffer. The experiment is to port a state-of-the-art, distributed-memory, dense matrix library, Elemental, to this architecture and gain insight from the experience. We show that programmability addressed by this library, especially the proper abstraction for collective communication, greatly aids the porting effort. This enables us to support a wide range of functionality with limited changes to the library code. Copyright © 2011 John Wiley & Sons, Ltd.