VLSI Implementation of a Complete Pipeline MMSE Detector for a 4 × 4 MIMO-OFDM Receiver

Authors:
Shingo Yoshizawa;Yasushi Yamauchi;Yoshikazu Miyanaga
Affiliations:
-;-;-
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2008

Citing 2
Cited 2

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Abstract

This paper presents a VLSI architecture of MMSE detection in a 4×4 MIMO-OFDM receiver. Packet-based MIMO-OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We propose a pipelined MMSE detector using Strassen's algorithms of matrix inversion and multiplication. This circuit achieves real-time operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and shows a potential for providing a 2.6-Gbps transmission speed in a 160-MHz signal bandwidth.