Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Performance-Effective and Low-Complexity Task Scheduling for Heterogeneous Computing
IEEE Transactions on Parallel and Distributed Systems
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Scalable Task Duplication Based Scheduling Algorithm for Heterogeneous Systems
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
Journal of Parallel and Distributed Computing
Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors
International Journal of High Performance Computing and Networking
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An energy-balanced task scheduling heuristic for heterogeneous wireless sensor networks
HiPC'08 Proceedings of the 15th international conference on High performance computing
Towards Energy Aware Scheduling for Precedence Constrained Parallel Tasks in a Cluster with DVFS
CCGRID '10 Proceedings of the 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing
Enhanced Energy-Efficient Scheduling for Parallel Applications in Cloud
CCGRID '12 Proceedings of the 2012 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (ccgrid 2012)
Energy-aware parallel task scheduling in a cluster
Future Generation Computer Systems
Energy-Aware Scheduling on Multicore Heterogeneous Grid Computing Systems
Journal of Grid Computing
| Hi-index | 0.00 |
We propose a schedule named Low Power Heterogeneous Makespan (LPHM) that attempts to minimize makespan as well as power consumption in the execution of any directed acyclic task graph on heterogeneous processors. We combine the techniques of Heterogeneous Earliest Finish Time (HEFT) [9] and voltage scaling [4]. The processors used for execution are considered to be continuously voltage scalable within the range of operation. After initial scheduling for minimum makespan, the processors are voltage scaled down to reduce power consumption whenever there is an idle time. This voltage scaling is performed without violating the precedence relationships among tasks. The simulation results show power savings of 22% over HEFT with no increase in makespan.