A Heuristic for reducing dynamic power dissipation in clocked sequential designs

Authors:
Noureddine Chabini
Affiliations:
Department of Electrical and Computer Engineering, Royal Military College of Canada, Kingston, ON, Canada
Venue:
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Year:
2007

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Abstract

Assigning computational elements to low supply voltages can reduce dynamic power dissipation, but increase execution delays. The problem of reducing dynamic power consumption by assigning low supply voltages to computational elements off critical paths is NP-hard in general. It has been addressed in the case of combinational designs. It becomes more difficult in the case of clocked sequential designs since critical paths are defined relative to the position of registers. By repositioning some registers, some computational elements could be moved from critical paths, and hence their supply voltages can be scaled down. In this paper, we propose a polynomial time algorithm to determine solutions to this problem in the case of clocked sequential designs. Experimental results have shown that the proposed algorithm is able to significantly reduce dynamic power dissipation.