Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages

Authors:
Abdulkadir U. Diril;Yuvraj S. Dhillon;Abhijit Chatterjee;Adit D. Singh
Affiliations:
Georgia Institute of Technology;Georgia Institute of Technology;Georgia Institute of Technology;Auburn University
Venue:
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Year:
2005

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Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Usage of dual supply voltages in a digital circuit is an effective way of reducing power consumption due to the quadratic relation of supply voltage to power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of applying dual supply voltages at gate level granularity without using level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCASý85 benchmark circuits.