A dual-edge triggered phase detector for fast-lock DLL

  • Authors:

  • Kyung Ho Ryu;Sang Kyu Park;Seong-Ook Jung

  • Affiliations:

  • School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea;School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea;School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea

  • Venue:
  • ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
  • Year:
  • 2008

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Abstract

DLL is used as a clock generator due to its stable operation and relatively simple design. Analog DLL has the advantages of lower phase offset and lower clock jitter than digital DLL. However, locking speed is slow in analog DLL. This paper proposes a dual edge triggered phase detector to enhance the locking speed of analog DLL and suggests a closed-form expression of locking speed which can correctly estimate the locking speed. Simulation results show that the locking speed of DLL, which includes the proposed phase detector, is 2-2.5 times better than that of DLL, which includes a single edge triggered phase detector.