Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2003 international symposium on Low power electronics and design
Thermal and Power Management of Integrated Circuits (Series on Integrated Circuits and Systems)
Thermal and Power Management of Integrated Circuits (Series on Integrated Circuits and Systems)
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Thermal analysis of 8-T SRAM for nano-scaled technologies
Proceedings of the 13th international symposium on Low power electronics and design
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Strong temperature dependence of leakage has been a major problem during burn-in test where increased voltages and temperatures are applied to weed out defective parts. Moreover, process variations may result in different temperature profiles in different dies during burn-in. This paper proposes an adaptive design-for-burn-in technique that stabilizes the junction temperature by controlling the leakage power using sleep (supply-gating) transistors for a wide range of ambient temperatures, process variations, thermal resistances and supply voltages.