Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates
Proceedings of the 2004 international symposium on Low power electronics and design
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This paper presents a behavioral model of a delay-locked loop (DLL) used to generate the timing signals in an integrated ultra wide-band (UWB) impulse radio (IR) system. The requirements of these timing signals in the context of UWB-IR systems are reviewed. The behavioral model includes a modeling of the various noise sources in the DLL that produce output jitter. The model is used to find the optimum loop filter capacitor value that minimizes output jitter. The accuracy of the behavioral model is validated by comparing the system level simulation results with transistor level simulations of the whole DLL.