Comparing algorithm for dynamic speed-setting of a low-power CPU
MobiCom '95 Proceedings of the 1st annual international conference on Mobile computing and networking
The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Power conscious fixed priority scheduling for hard real-time systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Soft timers: efficient microsecond software timer support for network processing
Proceedings of the seventeenth ACM symposium on Operating systems principles
Voltage scheduling in the IpARM microprocessor system
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Improving dynamic voltage scaling algorithms with PACE
Proceedings of the 2001 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Thread-level parallelism and interactive performance of desktop applications
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Dynamic voltage scaling on a low-power microprocessor
Proceedings of the 7th annual international conference on Mobile computing and networking
Automatic performance setting for dynamic voltage scaling
Proceedings of the 7th annual international conference on Mobile computing and networking
Real-time dynamic voltage scaling for low-power embedded operating systems
SOSP '01 Proceedings of the eighteenth ACM symposium on Operating systems principles
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
The Psychology of Human-Computer Interaction
The Psychology of Human-Computer Interaction
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems
RTAS '00 Proceedings of the Sixth IEEE Real Time Technology and Applications Symposium (RTAS 2000)
Real-Time Task Scheduling for a Variable Voltage Processor
Proceedings of the 12th international symposium on System synthesis
Policies for dynamic clock scheduling
OSDI'00 Proceedings of the 4th conference on Symposium on Operating System Design & Implementation - Volume 4
Balancing power consumption in multiprocessor systems
Proceedings of the 1st ACM SIGOPS/EuroSys European Conference on Computer Systems 2006
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The user in experimental computer systems research
Proceedings of the 2007 workshop on Experimental computer science
The user in experimental computer systems research
ecs'07 Experimental computer science on Experimental computer science
PICSEL: measuring user-perceived performance to control dynamic frequency scaling
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
An Energy Efficient Middleware Architecture for Processing Spatial Alarms on Mobile Clients
Mobile Networks and Applications
Hi-index | 0.00 |
Combining high performance with low power consumption is becoming one of the primary objectives of processor designs. Instead of relying just on sleep mode for conserving power, an increasing number of processors take advantage of the fact that reducing the clock frequency and corresponding operating voltage of the CPU can yield quadratic decrease in energy use. However, performance reduction can only be beneficial if it is done transparently, without causing the software to miss its deadlines. In this paper, we describe the implementation and performance-setting algorithms used in Vertigo, our power management extensions for Linux. Vertigo makes its decisions automatically, without any application-specific involvement. We describe how a hierarchy of performance-setting algorithms, each specialized for different workload characteristics, can be used for controlling the processor's performance. The algorithms operate independently from one another and can be dynamically configured. As a basis for comparison with conventional algorithms, we contrast measurements made on a Transmeta Crusoe-based computer using its built-in LongRun power manager with Vertigo running on the same system. We show that unlike conventional interval-based algorithms like LongRun, Vertigo is successful at focusing in on a small range of performance levels that are sufficient to meet an application's deadlines. When playing MPEG movies, this behavior translates into a 11%--35% reduction of mean performance level over LongRun, without any negative impact on the framerate. The performance reduction can in turn yield significant power savings.