Noise-tolerant high fan-in dynamic CMOS circuit design

Authors:
Walid Elgharbawy;Pradeep Golconda;Magdy Bayoumi
Affiliations:
University of Louisiana at Lafayette, Lafayette, LA;University of Louisiana at Lafayette, Lafayette, LA;University of Louisiana at Lafayette, Lafayette, LA
Venue:
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Year:
2005

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Abstract

Scaling CMOS technology to next generation improves performance, increases transistor density, and reduces power consumption per device. However, scaling also increases the subthreshold leakage current which greatly degrades the circuit's noise immunity. In this paper we propose a new circuit technique that makes domino dynamic CMOS more robust and more noise-tolerant with minimal performance degradation and energy overhead. Simulations for high fan-in gates show a noise immunity improvement of 2.13X using Berkeley Predictive Technology Models (BPTM) of 70nm with minimal performance and power degradations over standard domino circuits.