On-chip detection methodology for break-even time of power gated function units

Authors:
Kimiyoshi Usami;Yuya Goto;Kensaku Matsunaga;Satoshi Koyama;Daisuke Ikebuchi;Hideharu Amano;Hiroshi Nakamura
Affiliations:
Shibaura Institute of Technology, Tokyo, Japan;Shibaura Institute of Technology, Tokyo, Japan;Shibaura Institute of Technology, Tokyo, Japan;Shibaura Institute of Technology, Tokyo, Japan;Keio University, Yokohama, Japan;Keio University, Yokohama, Japan;The University of Tokyo, Tokyo, Japan
Venue:
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Year:
2011

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Abstract

In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the minimum required time i.e. the break-even time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.