Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits
IEEE Transactions on Computers
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
High speed CMOS design styles
Testing of Digital Systems
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On circuit techniques to improve noise immunity of CMOS dynamic logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Charge-sharing alleviation and detection for CMOS domino circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Domino CMOS circuits are an option for speeding up critical units. An inherent problem of Domino logic is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of a circuit can violate the noise margins and cause erroneous responses at the output. The dominant solution to this problem is the multiple precharging of the gate's internal nodes. However, the added precharge transistors are not testable for stuck-open faults. Undetectable stuck-open faults at these transistors may cause noise margins reduction and consequently may affect the reliability of the circuit since its operation in the field will be sensitive to environmental factors such as noise. In this paper, we propose new multiple precharging design schemes that enhance Domino circuits' testability with respect to transistor stuck-open and stuck-on faults.