Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
LUSTRE: a declarative language for real-time programming
POPL '87 Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
A machine program for theorem-proving
Communications of the ACM
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
A proof engine approach to solving combinational design automation problems
Proceedings of the 39th annual Design Automation Conference
Symbolic Model Checking
A Tutorial on Stålmarcks's Proof Procedure for Propositional Logic
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Model-Based Synthesis of Fault Trees from Matlab-Simulink Models
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
A SAT Based Approach for Solving Formulas over Boolean and Linear Mathematical Propositions
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
Combination of Fault Tree Analysis and Model Checking for Safety Assessment of Complex System
EDCC-4 Proceedings of the 4th European Dependable Computing Conference on Dependable Computing
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Symbolic fault tree analysis for reactive systems
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
On the adoption of model checking in safety-related software industry
SAFECOMP'11 Proceedings of the 30th international conference on Computer safety, reliability, and security
Model-based multi-objective safety optimization
SAFECOMP'11 Proceedings of the 30th international conference on Computer safety, reliability, and security
Automatic generation of hardware/software interfaces
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
IFM'05 Proceedings of the 5th international conference on Integrated Formal Methods
Using deductive cause-consequence analysis (DCCA) with SCADE
SAFECOMP'07 Proceedings of the 26th international conference on Computer Safety, Reliability, and Security
Modeling a BSG-E automotive system with the timing augmented description language
ISoLA'12 Proceedings of the 5th international conference on Leveraging Applications of Formal Methods, Verification and Validation: applications and case studies - Volume Part II
Science of Computer Programming
Formal component-based modeling and synthesis for PLC systems
Computers in Industry
ILPc: a novel approach for scalable timing analysis of synchronous programs
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Observations on formal safety analysis in practice
Science of Computer Programming
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As safety critical systems increase in size and complexity, the need for efficient tools to verify their reliability grows. In this paper we present a tool that helps engineers design safe and reliable systems. Systems are reliable if they keep operating safely when components fail. Our tool is at the core of the Scade Design Verifier integrated within Scade, a product developed by Esterel Technologies. Scade includes a graphical interface to build formal models in the synchronous data-flow language Lustre. Our tool automatically extends Lustre models by injecting faults, using libraries of typical failures. It allows to perform Failure Mode and Effect Analysis, which consists of verifying whether systems remain safe when selected components fail. The tool can also compute minimal combinations of failures breaking systems' safety, which is similar to Fault Tree Analysis. The paper includes successful verifications of examples from the aeronautics industry.