Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Proceedings of the Fourth Annual Symposium on Logic in computer science
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Property preserving abstractions for the verification of concurrent systems
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
Formal Methods in System Design - Special issue on symmetry in automatic verification
Software reliability methods
Verification model reduction through abstractions
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Efficient Computation of Recurrence Diameters
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Partial-Order Methods for Temporal Verification
CONCUR '93 Proceedings of the 4th International Conference on Concurrency Theory
Parallel Execution of Stochastic Search Procedures on Reduced SAT Instances
PRICAI '02 Proceedings of the 7th Pacific Rim International Conference on Artificial Intelligence: Trends in Artificial Intelligence
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Stubborn sets for reduced state space generation
Proceedings of the 10th International Conference on Applications and Theory of Petri Nets: Advances in Petri Nets 1990
Successive Approximation of Abstract Transition Relations
LICS '01 Proceedings of the 16th Annual IEEE Symposium on Logic in Computer Science
Journal of Computer Science and Technology
Bounded Semantics of CTL and SAT-Based Verification
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Model checking with SAT-based characterization of ACTL formulas
ICFEM'07 Proceedings of the formal engineering methods 9th international conference on Formal methods and software engineering
Verification of ACTL properties by bounded model checking
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
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Bounded model checking (BMC) based on satisfiability testing (SAT) has been introduced as a complementary technique to BDD-based symbolic model checking of LTL properties in recent years and a lot of successful work has been done with this approach. The basic idea is to search for a counter example of a particular length and to generate a propositional formula that is satisfied iff such a counter example exists. An over approximation of the length that need to be checked in order to certify that the system is error free is usually too big, such that it is not practical to use this approach for checking systems that are error free with respect to given properties. Even if we know the exact threshold, for a reasonably large system, this threshold would possibly also be large enough to make the verification become intractable due to the complexity of solving the corresponding SAT instance. This study is on a different direction and the aim of this study is verification of valid properties. We propose an approach to (partly) avoid the use of the completeness threshold as the verification criteria when checking systems that are error free with respect to LTL properties. The benefit of the use of this approach may be very large compared to the use of the completeness threshold. Though, Prasad, Biere and Gupta pointed out in a survey paper [19] that, currently, the strength of SAT-based verification techniques lies primarily in falsification, this study explores the strength of SAT-based techniques for verification and the case study shows that this is a promising approach.