Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Reasoning about infinite computations
Information and Computation
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Symbolic Model Checking
Model Checking of Safety Properties
Formal Methods in System Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Efficient LTL compilation for SAT-based model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Symbolic algorithmic verification of generalized noninterference
WSEAS Transactions on Computers
SAT-based compositional verification using lazy learning
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Axiomatizing extended temporal logic fragments via instantiation
ICTAC'07 Proceedings of the 4th international conference on Theoretical aspects of computing
Automatic analysis of DMA races using model checking and k-induction
Formal Methods in System Design
Software verification using k-induction
SAS'11 Proceedings of the 18th international conference on Static analysis
Automatic analysis of scratch-pad memory code for heterogeneous multicore processors
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Tightening test coverage metrics: a case study in equivalence checking using k-induction
FMCO'10 Proceedings of the 9th international conference on Formal Methods for Components and Objects
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The work presented in this paper addresses the challenge of fully verifying complex temporal properties on large RTL designs. Windowed induction has been proposed by Sheeran, Singh, and Stalmarck as a technique augmenting Bounded Model Checking for unbounded verification of safety properties. While induction proved to be quite effective for combinational properties, the case of temporal properties was not handled by previously known methods. We introduce explicit induction, a new induction scheme targeted to temporal properties, and to interactive development of inductive proofs. The innovative idea in explicit induction is to make the induction scheme an explicit part of the specification, where it can be easily controlled, using a highly expressive language like ForSpec. We show how explicit induction was implemented with minor modifications in the ForSpec compiler and in Thunder, a bounded model checker. Finally, we describe how explicit induction was used for verifying large control circuits with extensive feedback in the Pentium^T^M4 processor. The circuits verified by explicit induction are orders of magnitude larger than those verifiable by traditional model checking approaches.