Automatic and efficient simulation of operation contracts
GPCE '10 Proceedings of the ninth international conference on Generative programming and component engineering
Proceedings of the 38th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Computing small unsatisfiable cores in satisfiability modulo theories
Journal of Artificial Intelligence Research
MDG-SAT: an automated methodology for efficient safety checking
International Journal of Critical Computer-Based Systems
URBiVA: uniform reduction to bit-vector arithmetic
IJCAR'10 Proceedings of the 5th international conference on Automated Reasoning
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We present a new decision procedure for finite-precision bit-vector arithmetic with arbitrary bit-vector operations. Such decision procedures are essential components of verifications systems, whether the domain of interest is hardware, such as in word-level bounded model-checking of circuits, or software, where one must often reason about programs with finite-precision datatypes. Our procedure alternates between generating under- and over-approximations of the original bit-vector formula. An under-approximation is obtained by a translation to propositional logic in which some bit-vector variables are encoded with fewer Boolean variables than their width. If the under-approximation is unsatisfiable, we use the unsatisfiable core to derive an over-approximation based on the subset of predicates that participated in the proof of unsatisfiability. If this over- approximation is satisfiable, the satisfying assignment guides the refinement of the previous under-approximation by increasing, for some bit-vector variables, the number of Boolean variables that encode them. We present experimental results that suggest that this abstraction-based approach can be considerably more efficient than directly invoking the SAT solver on the original formula as well as other competing decision procedures.